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Altera_Forum's avatar
Altera_Forum
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9 years ago

Arria V hold time violations

I am getting some hold time violations reported in my ArriaV design and I am trying to make sense of the TimeQuest report. The violations are buried down in a VIP IP block in my Qsys subsystem. When I run the timequest analysis it reports a number of hold time violations. Looking at the timing report for an offending path, it appears as though there is a much larger clock skew between two nearly adjacent elements than I would expect (even after pessimism is removed). See attached diagram showing timing report and path location. Is this much clock skew (600+ ps) really expected between two elements so close together on the die? Is there anything I can do about it, given that the failing path is within a VIP core?

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Strange. It's possible to have large hold because the global is a large H tree, so you could have two nodes next to each other, but they may be at very different paths fed by the clock tree. The router can add delay to a path to meet hold violations and this is normally not a problem, but in your case a dedicated path between the DSPs is being used so there is no way for the router to add delay. I have never seen this problem(and have seen a million ways to have hold violations), so am surprised this hasn't come up before. I wonder if it occurs at the Y# -> Y# location that it occurs at, but it would be difficult to avoid DSP chains from crossing this point. (Arria V has a number of high-DSP designs, so again, I am surprised this hasn't been seen before and i feel like I'm missing something.)

    Sorry I don't have a solution, but just helping with the analysis.