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MKark1
New Contributor
7 years agoArria 10 SoC Serdes Error
Hi, I am in the early stages of my design working on Schematic verification. I am working on Arria 10 SoC 10AS066K2F40E1HG in Quartus Prime Pro 17.1 my design contains a high speed ADC which gives ...
IDeyn
Contributor
7 years agoHi MKark1!
I've just downloaded and inspected your project.
You see that error message:
"Error(18805): No dedicated path available for refclk signal, FMC3_ADC5_DACLK_P. Please promote your refclk to a global clock or move it to a dedicated IOPLL refclk pin. (1 location affected) "
You have to replace PIN_AK10 to a dedicated clock pin, because you want to use PLL and PLL's clock input need to be driven by dedicated clock input.
You can see that inside the bank there is another didicated clock pair - pins AU7-AT7 - you have to choose them instead.
Hope that helps.
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Best regards,
Ivan