Forum Discussion

MKark1's avatar
MKark1
Icon for New Contributor rankNew Contributor
6 years ago

Arria 10 SoC Serdes Error

Hi, I am in the early stages of my design working on Schematic verification. I am working on Arria 10 SoC 10AS066K2F40E1HG in Quartus Prime Pro 17.1 my design contains a high speed ADC which gives ...
MKark1's avatar
MKark1
Icon for New Contributor rankNew Contributor
6 years ago

Hi @IDeyn​ ,

with your suggestions, I was able to solve the error.

In my schematic, I have a total of 8 ICs of my ADC. So total of 16 channels are mapped. In 1 IO bank, total 4 channels of 2 ADCs are mapped . When I try to generate the design with 2 SERDES IPs in the same bank, the fitter is unable to fit the design. My question is will one bank support only 1 SERDES at max?

Also, If i want to map the clock from ADC to a non-clock pin, is it possible to force the fitter to accept the assignment by constraints?

Attached is my updated project.

Regards,

Mihir