Arria 10 SoC Serdes Error

Hi @IDeyn​ ,

The outputs of my ADC (partno: ADS42LB69) are differential. the template instantiation in VHDL requires std_logic_vector as input where each bit corresponds to 1 bit (P and N together make 1 bit, correct me if I am wrong). So I couldn't find a way to directly connect differential pins of the ADC to the SERDES IP. Hence, I have used Alt_INBUF_DIFF.

Also, regarding clock, I am feeding the output clock from the ADC to the SERDES IP. My design fails in the synthesis stage itself. So I believe the issue is in the code somewhere rather than pin assignment. anyways, you can still check the pin planner, assigned pins are clock capable.

Have a look at my attached project.

Thanks in Advance.

Regards,

Mihir