arrays

1)

architecture a of t is
type arr is array (natural range <>) of std_logic_vector(N downto 0) ;
signal rr : arr(M downto 0) := (others => (others => '0')) ;
...

2) this doesn't work without a package because a port of array type has to be fully constrained (at least in VHDL 93, see later). An alternative is to use the std_logic_2D data type , declared in the lpm package as

type std_logic_2D is array (natural range<> , natural range <>) of std_logic ;

This you can use in your entity:

library lpm ;
use lpm.lpm_components.all ;  -- or use lpm.lpm_components.std_logic_2D
entity t is
generic (
  M : natural := 4 ;
  N : natural := 2
  ) ;
port (
  ...
  result : std_logic_2D(M - 1 downto 0 , N - 1 downto 0) ;
  ...
  ) ;
end entity t ;

If you have a utility package you include in your projects (I do) you could add the std_logic_2D declaration there in stead of relying on the lpm package

Slicing and assigning values is tedious though and you may have to write (quite a few) functions and procedures in your utility package to handle that all.

There is an alternative in VHDL 2008 that let's you define an array of unconstrained std_logic_vector:

type arr_slv is array (natural range <>) of std_logic_vector ; 

You would again add this declaration in your utility package, which you could use like this :

use work.my_utility_package.all ;
entity t is
generic (
  M : natural := 4 ;
  N : natural := 2
  ) ;
port (
  ...
result	: out  arr_slv( M - 1 downto 0 )(N - 1 downto 0 ) ;
 ...
  ) ;

I'm not sure whether ModelSim handles that, Quartus II should as it did so already in version 10.0. Unfortunately I have to stick with the std_logic_2D as I have too much legacy source code to convert otherwise

Unconstrained 2d arrays are part of the VHDL 2008 spec, and modelsim 10+ should handle them fine. VHDL 2008 also allows you to declare types, functions, procedures etc in the generic region, but I doubt Quartus will bother supporting this any time soon. So you will need a package (which is usually the most sensible thing anyway). Any reason you dont want a package?

I would personally avoid std_logic_2d type because of what josyb has said - it can cause a lot of hassle and you need conversion functions to break your arrays out of there.

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Unconstrained 2d arrays are part of the VHDL 2008 spec, and modelsim 10+ should handle them fine. VHDL 2008 also allows you to declare types, functions, procedures etc in the generic region, but I doubt Quartus will bother supporting this any time soon.

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I'm not so sure about ModelSim either, e.g. it doesn't handle the if generate-else generate construct. It does handle std_logic_2D flawlessly.

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So you will need a package (which is usually the most sensible thing anyway). Any reason you dont want a package?

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Packages where you constrain otherwise 'generic' objects are a hassle too as you have to do that on a project basis, which is OK for the project specific types but not nice if you then want to call a generic module. E.g you could have a n x n kernel with a std_logic_2D output which you then feed into a generic summation module. If you use a package-constrained type you have to write a wrapper around the code (not sure this always works) or even worse change the source code on a per project basis replicating copies everywhere.

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I would personally avoid std_logic_2d type because of what josyb has said - it can cause a lot of hassle and you need conversion functions to break your arrays out of there.

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I have written a lot of std_logic_2D functions taking the hassle out of std_logic_2D.

If you look at VHDL from a more purist view, the 2D-array is, IMHO, a more 'natural' object then what is commonly called a 1Dx1D type. I lately experimented with 3D and 4D objects which both ModelSim and Quartus handle fine.

Altera uses the std_logic_2D originated to represent the double array in AHDL: arr[][] as used in e.g. lpm_mux.