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But i have to read out multiple values of these data tables simultaneously and asynchroneously in various different code locations
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In general, there's no such thing as asynchronous inside the FPGA :)
Your FPGA is a clocked device, perhaps with multiple clocks, eg., one for each of your external devices. Your system needs some form of control path, eg., the VME backplane or 1GbE connections to all the boards. This interface would provide control and command, eg., downloading of filter coefficients, monitoring of voltages and currents. Data travels via multiple synchronous domains, with clock crossing logic between each domain.
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(the contents are i.e. parameters for pedestal and threshold corrections of the analog values of the individual silicon sensor strips, and later also e.g. for FIR-filter-parameters etc..., and there are multiple stages of these corrections which use the same tables...), so i think that normal dual-ported RAM does not work here. Whenever possible, I of course use optimized RAMs as found in alteras design recommendations.
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You have two choices for your RAM; single-ported or dual ported, and that's it. It either works for your application or it does not. The trick is finding a way to make it work :)
For example, keep in mind that the FPGA memory can operate at several hundred MHz. If your multiple sensors require the same RAM contents at a slower rate, the RAM can simply be read multiple times. For example, lets say all sensors need to be updated at 100Hz. The sensors each use a 32-bit parallel word, and that word comes from a RAM. There are 100 sensors to simultaneously update with a different value, and because all the values you need can fit in a single RAM, you only want to use a single RAM (not 100 RAMs). The way to implement this is to have each sensor use a double-buffered register; one register with the current value, another register to store the next value to use. The next value gets loaded at 100Hz rate by a global control signal, eg., something derived from a GPS tick (i.e., the register-to-register path has an enable control that pulses every 100Hz). The task of the RAM-to-sensor register interface is to update the double-buffered next register within the next 100MHz period, i.e., as soon as that double buffered register has transferred to the "in-use" register, a control FSM will go and update the 100 other values. The requirement is to read 100 RAM locations and write them to 100 registers. The implementation that requires the minimum resources is to configure the 100 "next" registers as a shift register, as then it take 100 clocks at the memory rate to update the next value.
The key to FPGA design is to first determine what needs to happen, then jot down a few ideas, synthesize some of those ideas to see how many resources are being used and whether it has good timing margin (which indicates a poor design, i.e.., poor in the sense that it does not map well to FPGA resources).
Drawing a block diagram is a good start. Asking questions, or presenting your ideas clearly for others to review is also a good way to get feedback.
Cheers,
Dave
Honored Contributor
