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well... i have a system of 48 Altera Stratix IV here, where i am co-developing the electronics, and where i am supposed to develop the firmware now, why i started learning VHDL a few months ago :-), and the only thing of my now about-6000-lines-code i programmed and tested all the time, with interfaces (e.g. I2C and SPI to a lot of peripheral systems), busses (e.g. 48 highspeed-ADCs per Stratix with DDR-serial-interfaces, DSPs, LVDS-Interfaces plus substantial protocols to other FPGAs (cyclone II, ...), a VME bus system, and lots of more stuff...) which now does not compile and synthesize are just these memory arrays, cause i simply dont know yet how to instantiate them correctly, and i dont find any information how to do it :-)
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Why don't you explain your system to me, and what you want to do with it, and I'll try to help provide some direction for you.
I have a lot of experience with large FPGA-based systems; the system I am working on uses 250 Stratix IV GTs.
If you don't want to discuss the project on this list, then send me an email (to my forum name).
Cheers,
Dave
Honored Contributor
