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Altera_Forum
Honored Contributor
12 years agoIf your data types are located in a package, and that package is used in each VHDL file, then there should be no problem.
Write and test your code in Modelsim first. Quartus will not synthesize VHDL that does not map to hardware. Your description sounds like "simulation-only" VHDL. If you need to implement your logic in hardware, then you have to code appropriate to the hardware. Cheers, Dave