Honored Contributor
Honored Contributor1. in the BDF, a 2d array will come from something like: packets_in[0..17][63..0]. Your VHDL commands_array type will look like a 2d array in quartus in the BDF, and will generate it as such, as you have seen. To avoid this - dont use BDF (its all a throwback to AHDL, and none of us need that headache anymore). Do yourself a favour and make your design more portable and version control friendly by removing all use of BDF.
2. This is probably because the net has been renamed or merged. It's usually best to search for post-synthesis nets as these will be the ones that really exist. For example, it tends to keep entity output names, so if you connected my_block_out to some_other_block_in, the latter name will probably be removed. If you add the latter in signaltap, my experience is that it will show up as red in the final compiled version as a net that no longer exists. There are way around this. There are some attributes to try and preserve nets and zero fan out registers (debug logic you only want connected to signaltap for example). These are noprune for nets http://quartushelp.altera.com/14.1/mergedprojects/hdl/vhdl/vhdl_file_dir_noprune.htm and preserve for registers with no fanout http://quartushelp.altera.com/14.0/mergedprojects/hdl/vhdl/vhdl_file_dir_preserve.htm
