Honored Contributor
Honored Contributor1. Well, I defined the array as a 1-d array of vectors in a package (like I've shown in the first post) and defined the problematic ports as 1-d arrays as well, inside the VHDL files themselves (never heard of defining an array in a BDF file, so I'm not sure I understand you).
Unfortunately I can't really avoid that, because I make an HDL file from a BDF for the purpose of simulating in Modelsim. Is there something I can do so that Quartus will not convert the arrays to 2-d? 2. About the SignalTap, I haven't read it anywhere :) - I'm speaking from experience. I declared a signal, assigned it to be something in the architecture and not a process (a < '1' when x = '1' else '0', for example, where a is the signal I want to monitor) and wasn't able to find it in SignalTap. I put it in a process and next thing I know, I see it. I tried to do that again to make sure I'm not mistaken, and it happened again. I should mention I'm working with Quartus 13.0 sp1, because I need support for the DE2. Maybe it's a bug? I honestly thought maybe it's because I don't understand logic analyzers. Also, when searching for signals/pins, I always use design entry (all names) as my filter. I understand why you would think my logic is outputting 0 but I can assure you it's not. The 8-bit vectors eventually go to a UART module I made that converts the data to serial, and from there it's sent to servos. Not only do I see in SignalTap that my logic's output is fine (like the serial output), but the servos themselves are working perfectly. I can prove it to you if you wish by attaching a screenshot :)
