Arrays - detect signal changes and simulate in Modelsim

1. Commands_array, is a 1D array, but you're trying to declare packets_in as a 2D array. because the commands_array type (usual convention is to pre/post pend type names with _t or _type to avoid confusion with signals/variables etc) already has 64 bit slv's declared, there is no need to declare the size of them.

In vhdl 2008, it is legal to a declare array types of an unconstrained array type, and then declare the length when you create the signal/variable. Something like:

  type commands_array_t is array (natural range <>) of std_logic_vector;
  ...
  packets_in : in commads_array_t(0 to 17)(63 downto 0);

this should not be confused with 2d arrays, which use the syntax you're trying. But I would avoid 2d arrays here, as they are not sliceable.

  type commands_array_t is array (natural range <>, natural range <>) of std_logic; -- really not fun to use
  ....
  packets_in : in commands_array_t(0 to 17, 63 downto 0);

2. Is the signal marked as red? that means signatap could not find the net in the final design. Otherwise if it's black/blue and always zero - then it really is zero.