array problem

I added the missing definitions for a full design, and it infers internal RAM with Cyclone III and default synthesis settings in Quartus V9.0.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test1 is
port 
  (
    ds        : in std_logic;
    loc_addr   : in integer range 0 to 255;
    usb_rnw   : in std_logic;
    usb_din   : in unsigned(15 downto 0);
    usb_dout  : out unsigned(15 downto 0)
  );
end entity;
architecture rtl of test1 is
begin
usb_data : PROCESS(ds) is
TYPE RAM is array (0 to 255) of unsigned(15 downto 0);
variable config :RAM; 
variable ram_index :integer range 0 to 255; -- index into RAM array 
BEGIN
if(ds'EVENT AND ds ='1') then
if(usb_rnw = '1') then -- read from RAM output to USB
ram_index := loc_addr;
usb_dout <= config(ram_index);
else -- in from USB write to RAM
ram_index := loc_addr;
config(ram_index) := usb_din;
end if;
end if; -- main ds event
end process usb_data;
end;