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Altera_Forum
Honored Contributor
Honored ContributorArray of integer to std_logic_vector !?
Hello guys !
Description : the input is an std_logic_vector ..... the outpout must be an std_logic_vector BUT, I read every element of the input and check if it is '1' then write 1 to an array else write -1 . the final array should be converted to an output which is an std_logic_vector !!!! For example INput : std_logic_vector (5 downto 0) :="010101"; ====> array = { -1 1 -1 1 -1 1} OUTput : std_logic_vector (5 downto 0); What are the possible solution to go from array to my output?!!!3 Replies
Altera_ForumThat sounds like a crazy idea. Why are you converting a 6 bit bus into a 12 bit bus (2 bits is required to cover 1 and -1) AND the original 6 bit data. Im guessing you're trying to find the number of 1s compared to number of 0s?
anyway you can easily do it.type int_array_t is array(5 downto 0) of integer range -1 to 1; signal my_ar : int_array_t; ... for i in my_ar'range loop if input(i) = '0' then my_ar(i) = -1; elsif input(i) = '1' then my_ar(i) = 1; else --cover illegal states in simulation my_ar(i) = 0; end if; end loop;- Altera_Forum
Obviously it is easy to do the 1 and -1 statements, I've already did it, BUT my problem is with the output of 12 bits !!! How to do it ?!
- Altera_Forum
convert the integer to the signed type:
Ill let you work out the arrays of 12 bits etc as I assume this is some assignment. There are plenty of VHDL tutorials out there.use ieee.numeric_std.all;; op : out signed(1 downto 0); op <= to_signed(some_integer, op'length);
