Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Array of integer to std_logic_vector !?

Hello guys ! Description : the input is an std_logic_vector ..... the outpout must be an std_logic_vector BUT, I read every element of the input and check if it is '1' then write 1 to an arra...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

convert the integer to the signed type: 


use ieee.numeric_std.all;;
op : out signed(1 downto 0);
op <= to_signed(some_integer, op'length);

Ill let you work out the arrays of 12 bits etc as I assume this is some assignment. There are plenty of VHDL tutorials out there.