Array implementation in VHDL and calculating the average of elements in the array

I have a Home assignment to be done in VHDL to find out the average of the elements of an array and then subtract thrice the average from each of the array elements. Then the elements greater than zero must be made zero..I've written the following code in Xilinx ISE..I'm new to VHDL

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-- Company:

-- Engineer:

--

-- Create Date: 22:52:57 10/30/2012

-- Design Name:

-- Module Name: rem_trend - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity rem_trend is

end rem_trend;

architecture Behavioral of rem_trend is

type rem_trend is array(15 downto 0) of real;

sum = 0;

for j in 0 to length[rem_trend] loop

sum = sum+rem_trend[j];

end loop

sum = sum/length[rem_trend];

for i is 1 to 3 loop

for j is 0 to length[rem_trend] loop

rem_trend[j] = rem_trend[j]-sum;

end loop

end loop

for j is 0 to length[rem_trend] loop

if (rem_trend[j]>'0') then

rem_trend[j] = 0;

end if;

begin

end Behavioral;

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Any help in this regard will be worth a million thanks...I don't know why this doesn't work and what exactly I need to add?