Array en VHDL

Hi everybody !

library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cdm is 
port (
         clk : in std_logic ;
         rst : in std_logic  ;
         data: in std_logic  ;
        odata: out std_logic  ;
         CD  : in  std_logic_vector(15 downto 0) ;
        isis :out  integer range 0 to 3  ;
         S   :out std_logic_vector(3 downto 0 ));
end entity ;
architecture beh of cdm is 
    type tab is array(3 downto 0)of std_logic_vector(15 downto 0);
        
        signal i      :integer range 0 to 3 ;
        signal idata  :std_logic  ;
        signal itab :tab ;
        begin 
         code :process(clk,rst)
               begin 
                    if(rst='1')then 
                     itab(i)<="0000" ;
                    else 
                        if(clk'event and clk='1')then 
                          
                           itab(i)<= not(CD(15 downto 12)xor (data));
                           S(i)<=itab(i);
                           i<= i+1 ;
                           
                           itab(i)<=not(CD (11 downto 8) xor(data));
                            S(i)<=itab(i);
                            i<=i+1 ;
                            
                           itab(i)<=not( CD(7 downto 4) xor (data));
                            S(i)<=itab(i);
                            i<=i+1;
                            
                           itab(i)<=not( CD(3 downto 0) xor (data));
                            S(i)<=itab(i);
                            i<=i+1 ;
                           
                           
                           
                                   
                           if i=3 then 
                                 idata<=data ;
                            end if ;
                          end if ;
                       end if ;
                  end process ;
                  isis<=i;
                 
                 odata<=idata ;
   end architecture ;