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CBart19's avatar
CBart19
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7 years ago

Array data type conflicts with std_logic_vector definition.

I would like to use a arrays of standard logic vectors of two different lengths so I declare two new data types. type tx_vector is array (0 to 14) of std_logic_vector(17 downto 0); type rx_vecto...
RRomano001's avatar
RRomano001
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7 years ago

Hi CBart, just curios about:

Iq_Ref how and where is declared?

Rx Tx are different from.

What at lines 868 and few lines before 868 can fire there error.

Aggregate has 11 bit is Iq_ref a signed vector 11 bit long or in range?

If A_temp is an Std_logic vector why typecast aggregate of same type?

VHDL is strongly typed and rigid, also deterministic so I like that also if something require a lot of coding.

Try if this help clarify

http://www.bitweenie.com/listings/vhdl-type-conversion/

Regards

Roberto