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CBart19's avatar
CBart19
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6 years ago

Array data type conflicts with std_logic_vector definition.

I would like to use a arrays of standard logic vectors of two different lengths so I declare two new data types. type tx_vector is array (0 to 14) of std_logic_vector(17 downto 0); type rx_vecto...
CBart19's avatar
CBart19
Icon for New Contributor rankNew Contributor
6 years ago

It seems things work if I construct the arrays in two steps from std_logic elements.

type tx_vector is array (17 downto 0) of std_logic;

type rx_vector is array (25 downto 0) of std_logic;

type tx_array is array (natural range <>) of tx_vector;

type rx_array is array (natural range <>) of rx_vector;

I can then use the tx_array and rx_array.

Is there a reason for this?

This is not what I need. Ultimately, I need an array of std_logic_vectors.