Are there any plans to update the Cyclone 10 GX dev board collateral kit to work with recent versions of Quartus?

Hi SooYL, JGurn,

I've encountered the same problem with Cyclone 10 GX as well as with Arria 10 GX and i think there is a problem with Quartus Prime Pro 18.1.

I use TSE with LVDS Phy. Please see my pin planner screenshot for Arria 10 GX DevKit attached (The same thing for Cyclone 10 GX)

The reference clock is definitely in the same bank with rx and tx lines. But Quartus Pro 18.1 fitter says that it is not

Here are assignments for eth_ref_clk:

eth_ref_clk Location PIN_BD24 Yes

eth_ref_clk I/O Standard LVDS Yes system_top

eth_ref_clk Input Termination Differential No system_top

eth_ref_clk Global Signal Global Clock Yes system_top

Quartus 17.1 and 18.0 fitter finishes with no errors.

Qsys gives this warning:

system_bd_sys_ethernet.sys_ethernet: To prevent potential performance issues, please ensure the reference clock to the LVDS uses the dedicated reference clock input within the same I/O bank directly. Manual reference clock promotion is not recommended

May be we can perform manual clock promotion in this case? How can we do this?