Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

aoc cannot find valid licences file

Hello. I'm trying out compiling Altera OpenCL on a new workstation. After acquiring the license file and installing Quartus II and OpenCL SDK. I tried to compile some OpenCL.

But aoc refuses to do so with the following message.

marty@labpc:~$ aoc test.cl -o test --board c5soc
Could not acquire a valid license for the Intel(R) FPGA SDK for OpenCL(TM).
Error: Verilog generator FAILED.
Refer to test/test.log for details.

But I can launch Quartus successfully and I'm sure that I have OpenCL licences(It says so in Altera Licensing Center).

Why is this happning. How can i diagnose this?

OS: Ubuntu 16.04

CPU: Ryzen R7 1700X

15 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    If you get license error, the compilation will not start, so there will be no log.

    If you already tried creating a dummy interface and it still doesn't work, then there is probably no choice but to open a service request with Altera.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hello all,

    (...)

    BTW, I'm trying to compile for the HARP system.

    Best,

    Roberto

    --- Quote End ---

    Is this the name of the board make? If so, could you please give a link to their website? If not, what is the target board? Please take it into account that v. 17 of Quartus as well as of the OpenCL SDK are not compatible with every board supported by v. 16. For example, the highest version compatible with the Terasic DE1-SoC board is 16.1. Also, just to check this matter: you managed to compile a VHDL example, but did you try to program the FPGA on your board? If so, did you succeed?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Thanks for your comment, but I'm pretty sure that I'm using a compatible version. Yet, I only compiled the VHDL test, I didn't generate the bitstream or program the device. That would require me to do some extra work.

    With respect to the board, Intel-Altera produce a hybrid Xeon-FPGA system, which they offer to researchers for testing within the HARP program.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Make sure the "LM_LICENSE_FILE" path is correct in your bashrc. If you are using Quartus v17.0, but acquired your license before v17.0 was released, you might need to request a new license from Altera. We were using the same license all the way from v15.0, but v17.0 rejected those licenses, so we had to acquire new ones. Also if you are on the v17.0 branch, make sure you are using v17.0.2; the latest update claims to have fixed some issue with valid licenses being rejected.

    --- Quote End ---

    I suggest a sticky post with FAQ (Frequently asked questions) because the forum is crowded of this kind of issues. Also would be a good idea if we can make a guidelines in order to orient the persons to achieve the desired projects.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Thanks for your comment, but I'm pretty sure that I'm using a compatible version. Yet, I only compiled the VHDL test, I didn't generate the bitstream or program the device. That would require me to do some extra work.

    With respect to the board, Intel-Altera produce a hybrid Xeon-FPGA system, which they offer to researchers for testing within the HARP program.

    --- Quote End ---

    That extra work would just be to check the compatibility of Quartus 17 with your board. Concerning the OpenCL SDK and the BSP for your board, this document (https://communities.intel.com/docs/doc-112103) gives detailed installation instructions for the Xeon-FPGA system, but refers to v. 16.0.2 of both Quartus and the OpenCL SDK. Did you follow instructions given by a similar document yet updated to v. 17 of the software?