Anyway to find output ports on a clock in tcl?

You are right, normally I would just list the ports and be done with it.

However I want to use the board's previously declared generic port names as these are tied to the validated pad lists. (These are big FPGAs and I don't want to be manually editing them!)

The idea was to have the .sdc automatically figure out the serdes ports by the clock driving them and then constrain them. Apparently this is fairly common practice in the ASIC world.

A single bus would not be so bad - but we'll be ending up with 12 FPGAs with multiple buses.

But as it is looking now I may just have to buckle-down and enter all the ports using the grouping method you show. Sometimes the slow way is the quicker way...

The 10.0ns timing I blanket-applied to all the output ports above was just to put a timing path on everything so that 'get_timing_paths' can then filter out the correct '-from_clock [get_clocks CLK_G0X4]' '-to_port [get_ports *]' davka previously suggested.

The 10ns delay can be anything - I later remove it by 'remove_output_delay [all_outputs]'

The actual constraints are applied to my filtered new port list by:

set_output_delay $OMD -max -clock [get_clocks {AD2CK}] -add_delay $myPortList

Unfortunately, while it looks like I've figured out how to do this, when I put this all in the .sdc file TimeQuest errors out saying that 'get_timing_paths' is not a proper SDC command. :mad:

So I'm back to square one...