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Altera_Forum
Honored Contributor
14 years agoHi Rysc, Yes, this is a DDR source synchronous design. I'm trying to follow "Implementing_a_Source_Synchronous_Interface_v2.0.doc"
CLK_G0X4 is the generated clock on the output of the dll (4x the input clock). I do have another generated clock AD2CK on the actual output port with CLK_G0X4 as its master_clock (as described in the doc). The place where I got stuck was trying to set the OMD (Output Max Delay) on page 18 line 82: [get_ports {data_out*}] which does not work for my port list (the port names are a group of different names defined by the vendor) This is why I want to find all the output ports driven by this clock. It seemed simple at the time! I agree that 'set_output_delay 10.0 -max -clock [get_clocks {CLK_G0X4}] -add_delay [all_outputs]' is odd, but it does allow the following:set myPaths -to -npaths 1000]
foreach_in_collection path $myPaths {
lappend myPortList ]
}
set_output_delay $OMD -max -clock -add_delay $myPortListI'm not very happy with it and I really should remove the 10.0ns output_delays before they cause trouble elsewhere - and I'm sure they will!