--- Quote Start ---
For a design, if I want to reduce power consumption, one approach is pausing the clock toggle for a module which does not need to work in a specific period. In the design, I can use a AND gate whose inputs are clk and enable as:
assign clkin=clk&&enable;
but with this AND gate, the clock skew may be more serious and it will be more difficult to analyse. So I wonder whether there is a better approach to close the clock toggle but don't use the AND gate?
Thanks.
--- Quote End ---
Use a PLL and hold the PLL in reset.
Also, before you get too creative, try an example design to see just how much power you may save. With the clock gating using gates, the extra power you burn while the design is running can easily overwhelm the savings you think you get when it is off. The reason is that by using non-global resources for distributing a clock you're charging and discharging far more capacitance that you would if you left the clock free running to each load on low capacitance routing.
Kevin Jennings
Honored Contributor
