Any approach to close clock toggle?

Foreword:

A purely combinational clock gating scheme like that can also suffer from glitches.

If you really really need to use logic to gate clocks, use a module such as this:

http://quartushelp.altera.com/9.1/mergedprojects/verify/da/comp_file_rules_clock.htm

That said, it's usually best not use logic to gate clocks in FPGAs due to skew issues.

Option 1: Use ALTCLKCTRL blocks.

These exist at the top of the clock distribution networks and provide glitch free gating without skew penalty -- they're always there, weather you're using them or not.

Advanatge: you'll save power on everything, including the clock distribution tree itself

Drawback: you're limited by the number of clock trees you have in the FPGA.

Option 2: Use clock enables

Advantage: easy to use, no restrictions on number of enabled clocks

Disadvantage: the clock distribution network into the LABs will still draw power.

always @ (posedge clk, posedge reset) begin
if (reset) then 
// reset
else if (enable) then
// normal logic
end

And in general, read the Quartus Handbook chapter on power optimization.