Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

another SPI interface timing constraint question

This thread describes almost my exact situation: http://www.alteraforum.com/forum/showthread.php?t=48900 I have a SPI master state machine that runs at 96MHz (output of PLL from 24MHz exte...
David32's avatar
David32
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi,

I have pretty much the same question and would very much appreciate access to the files mentioned.

The links seem to be no longer valid however.

Could you please repost with updated links.

Thanks in advance.

David