Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

another SPI interface timing constraint question

This thread describes almost my exact situation: http://www.alteraforum.com/forum/showthread.php?t=48900 I have a SPI master state machine that runs at 96MHz (output of PLL from 24MHz exte...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

--- Quote Start ---

Tested and working in hardware. Can't thank you enough for the help!

--- Quote End ---

You are most welcome!

Cheers,

Dave
conmemsr's avatar
conmemsr
Icon for New Contributor rankNew Contributor
5 years ago

Hi ,

I trying to set proper IO constraints for SPI Master where SPI_CLK_O and SPI_MOSI are generated by an internal clock and SPI_CLK_O is a divide by 4 generated with internal fast clock as source.

Can you re-post the solution or share the PDF with the timing analysis.

Thanks

msr