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Altera_Forum
Honored Contributor
11 years agoanother SPI interface timing constraint question
This thread describes almost my exact situation: http://www.alteraforum.com/forum/showthread.php?t=48900 I have a SPI master state machine that runs at 96MHz (output of PLL from 24MHz exte...
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- I'm glad it looks like it will help - good luck! :) Cheers, Dave --- Quote End --- Dave - I used your generated clocks method and it worked great. The only problem I had was that the multicycle constraints were not working until I used [get_clocks {spi1_clk}] instead of just spi1_clk, where spi1_clk is my generated clock name for the external SPI clock. Now the waveforms in Timequest match the way the logic works exactly, and it's very cool that Timequest includes the SPI clock delay. Tested and working in hardware. Can't thank you enough for the help! Bob