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Altera_Forum
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11 years ago

another SPI interface timing constraint question

This thread describes almost my exact situation: http://www.alteraforum.com/forum/showthread.php?t=48900 I have a SPI master state machine that runs at 96MHz (output of PLL from 24MHz exte...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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Very generous, Dave - thank you! I scanned the pdf briefly and it looks very well written and matches what I'm doing. When I get a chance I'll update my constraints and post the results. Two generated clocks? I never would have figured that out.

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I'm glad it looks like it will help - good luck! :)

Cheers,

Dave