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Altera_Forum
Honored Contributor
Honored Contributoranother SPI interface timing constraint question
This thread describes almost my exact situation: http://www.alteraforum.com/forum/showthread.php?t=48900 I have a SPI master state machine that runs at 96MHz (output of PLL from 24MHz exte...
Altera_ForumHonored Contributor
Honored ContributorI did some timing analysis on Quad SPI flash here:
https://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.pdf https://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.zip The timing constraints files should be able to help you. Cheers, Dave
David32Occasional Contributor
Hi,
I have pretty much the same question and would very much appreciate access to the files mentioned.
The links seem to be no longer valid however.
Could you please repost with updated links.
Thanks in advance.
David
