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Altera_Forum
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10 years ago

another SPI interface timing constraint question

This thread describes almost my exact situation: http://www.alteraforum.com/forum/showthread.php?t=48900 I have a SPI master state machine that runs at 96MHz (output of PLL from 24MHz exte...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

In your statements can you try putting in -clock_fall:

set_output_delay -clock SPI_SCK -clock_fall -max 0 [get_ports {SPI_MOSI}]

etc...

for all the statements. Let me know if this changes anything.