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Altera_Forum
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11 years ago

another SPI interface timing constraint question

This thread describes almost my exact situation: http://www.alteraforum.com/forum/showthread.php?t=48900 I have a SPI master state machine that runs at 96MHz (output of PLL from 24MHz exte...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Something is definitely wrong with my constraints. I changed SPI_SCK to 16MHz (96MHz/6) and updated the create_generated_clock constraint accordingly, but the SPI_MISO input waveform in Timequest did not change at all. Waveform looks identical and the path still fails by 4ns.