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Honored ContributorAnother 10482 VHDL error
Hello folks. I am trying for the first time to ease into the Altera MegaWizard DDR3 controller and have written a small VHDL top-level module containing an instance of the DD3 controller from the Meg...
Altera_ForumHonored Contributor
Honored Contributorthat error indicates it is expecting a locally signal that hasnt been decalred.
Have you mapped something like this?
signal pll_ref_clk : std_logic; -- this is a local wire
pll_ref_clk => pll_ref_clk, -- this maps the port of the entity to the local wire
