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Altera_Forum
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8 years ago

Another 10482 VHDL error

Hello folks. I am trying for the first time to ease into the Altera MegaWizard DDR3 controller and have written a small VHDL top-level module containing an instance of the DD3 controller from the Meg...
Altera_Forum's avatar
Altera_Forum
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8 years ago

that error indicates it is expecting a locally signal that hasnt been decalred.

Have you mapped something like this? 


signal pll_ref_clk : std_logic; -- this is a local wire
pll_ref_clk   => pll_ref_clk,  -- this maps the port of the entity to the local wire

Your error would come around if you didnt declare the signal locally, even if the port name exists on the component.