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As part of a project for a class, I am supposed to create several different types of circuits using Verilog. After getting everything written, the last step is:
For each circuit, collect a summary of size, placement, timing, power analysis, etc
I have all my modules written, along with the respective test benches and have done the simulation using ModelSim. However, I'm at a loss on how to acquire this data. Can anyone point me in the right direction?
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I'm assuming you know how to run Quartus. If not, you'll have to start down that path first then come back to this
- Size: A metric here can be the number of logic cells used. This will be available in the Quartus report.
- Placement: You'll have to check to see what is meant by a 'summary of placement'. The output of Quartus will be a final design where everything is 'placed', what is not clear is what is meant to summarize that placement
- Timing: Again an output of Quartus, simply view the report. The typical metric that is used to benchmark a circuit is maximum clock frequency.
- Power analysis: An output of Quartus, but you have to first set this up using the Power Play Power Analyzer tool. One of the inputs to that will be a file that is output from a simulation run of the routed design. Once you get through all of that, the tool will give a summary of power consumption.
Kevin Jennings
Honored Contributor
