Honored ContributorHi,
It takes too long time(about 10 hours) to do the "analysis & synthesis" in my design which is not a large project. And I am sure there must be something wrong with my code. Which reasons can make the ''analysis & synthesis'' process slow down strongly? Some code that can not be synthesized? or something like that? My computer has intel duo2 CPU and DDR memory of 3G.
Honored ContributorI don't know whether any of these cases still exist, but there used to be special cases where memory inference didn't work or just wasn't supported, resulting in a large logic implementation that took a long time in synthesis. If Analysis & Synthesis did finally finish for you and gave a much larger result than you expected, check whether any of the large blocks of hierarchy should have used more memory and less logic resources.
Try synthesizing each of the top-level blocks separately. (Set the top-level entity in the General category of the Settings dialog box to each of these blocks one at a time.) If any of those takes too long to synthesize, then repeat the process on each block instantiated in that block. If your problem is isolated to one or a few particular blocks of hierarchy, you should be able to find it by synthesizing block by block.Honored ContributorHow large is the final design after synthesis? Usually when I've seen this, it's code that is extremely "large" and then synthesis is supposed to reduce everything. For example, I've seen code that is probably over a million LUTs(by whatever counting method of a LUT), and then gets reduced down by a factor of 20x after synthesis. This usually means a ton of "support logic" that isn't really necessary. Note that synthesis builds everything into gates first and then synthesizes down at that level. So, for example, let's say you had a table that had hundreds of thousands of locations, but you only used a small subset. Synthesis will build tons of gates to make the table, may spend hours doing so, and then at the end realize you only use a few a rip everything out. This is pretty much the way all synthesizers work, so you need to be cognitive of what you're building. I usually see this with really high level code.
Another quick thing I've seen make a difference is when people don't bound their types. For example an integer is a 32-bit value in VHDL, so if you don't bound it's size, we'll make it 32 bits large, and then later on realize you only use 5 of those bits and rip everything out. Finally, if you have a lot of hierarchy, start synthesizing other levels and look for problem spots.Honored ContributorThank you very much!
I will try synthesizing block by block to find the problem.
