Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

Hi Ranesh,

Based on internal engineering team, this is expected behavior but not bug:

Below is the expert explanation on the second example (s_outbytecount) and first example (s_in_empty):

s_output_data[d] <= s_in_data[((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) -: 8]; //vector_capture_v2.sv, line number 151

In this case, array index uses logic type variable "s_outbytecount", for which synthesis generates a circuit which ensures no out of bound error happens.

In original use case, when local param is used in the index operation, they are replaced with actual values in compile time, so all possible indices get generated which cause out of bound error during loop unrolling.

e.g.

s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8]

Here, c is running from 16 to 31. During loop unrolling, index value is generated for all values of c which causes out of range error.

Thanks,

Sheng