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Ranesh's avatar
Ranesh
Icon for New Contributor rankNew Contributor
3 years ago

Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

Hi, I have following error while Analysis & Synthesis using Qyartus 21.2 and 22.2: Error(13224): Verilog HDL or VHDL error at vector_capture.sv(143): index -8 is out of range [15:0] for 's_in_da...
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Ranesh,

I think it would be helpful if you can provide a stripped code example that shows the problem, without all unneeded project stuff and with irrelevant module instantiations commented out.

Regards
Frank