Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

Hi @Ranesh ,

In your updated code, there are differences between the lines 144 and 151.

Line 144:

s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8];

Line 151:

s_output_data[d] <= s_in_data[((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) -: 8];

For line 151, if change s_outbytecount to c_IN_DESC_BYTE_CNT also produce the error below:

Error(13224): Verilog HDL or VHDL error at vector_capture.sv(151): index 136 is out of range [15:0] for 's_in_data'

For line 144, if change c_IN_DESC_BYTE_CNT to s_in_empty and with previous if (c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty))), there'll be no error produced as well.

So you're comparing two different things. Let me know if you have any further concern.

Thanks,

Best Regards,

Sheng

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