Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

Hi @Ranesh ,

I further create a test case with minimized code.

I'm getting synthesis error Error(13224): Verilog HDL or VHDL error at test.sv(19): index -8 is out of range [15:0] for 's_in_data' as you mentioned before in Quartus Pro v21.2 check image:

I further test with Vivado v2022.1. I'm also getting the similar synthesis error [Synth 8-524] part-select [-1:-8] out of range of prefix 's_in_data' check image:

I further found out that the root cause is at variable s_in_empty in module vector_capture.sv. You can't use logic type s_in_empty in for loop if statement. If change the type of variable s_in_empty from logic to for example parameter, both Quartus and Vivado can successfully synthesis the code check image:

Therefore, I believe this is expected behavior.

Thanks,

Best Regards,

Sheng

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