Honored Contributor
Honored ContributorThank you HRZ!
I can offload the executable file into the FPGA board now and can run aocl diagnose successfully. However, I just run the execution file from the BSP of Altera and another issue is that while OpenCL SDK compiled the kernel code, it still can not generate the offloading executable file for FPGA even though we can offload the executable file for the FPGA: [root@localhost hello_world]# aoc -v device/hello_world.cl -o bin/hello_world.aocx --board de5a_net_i2 --report aoc: Environment checks are completed successfully. You are now compiling the full flow!! aoc: Selected target board de5a_net_i2 aoc: Running OpenCL parser.... aoc: OpenCL parser completed successfully. aoc: Compiling.... aoc: Linking with IP library ... +--------------------------------------------------------------------+ ; Estimated Resource Usage Summary ; +----------------------------------------+---------------------------+ ; Resource + Usage ; +----------------------------------------+---------------------------+ ; Logic utilization ; 19% ; ; ALUTs ; 10% ; ; Dedicated logic registers ; 10% ; ; Memory blocks ; 10% ; ; DSP blocks ; 5% ; +----------------------------------------+---------------------------; aoc: First stage compilation completed successfully. Error: Compiler Error, not able to generate hardware I followed the other thread in this forum: https://alteraforum.com/forum/showthread.php?t=55654 https://www.alteraforum.com/forum/showthread.php?t=55176 I tried the combination of vertion with upgrade as you mentioned in the threads above but still didn't work: 1. Quartus Prime Pro 16.1.0 and OpenCL SDK 16.1.0 2. Quartus Prime Pro 16.1.2 and OpenCL SDK 16.1.0 3. Quartus Prime Pro 16.1.2 and OpenCL SDK 16.1.2 The error in the log file "quartus_sh_compile.log" is as below: Error (15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design. Error (15744): In atom 'board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_sd.inst_twentynm_hssi_pma_rx_sd' Error (15744): The settings must match one or more of these conditions: Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( prot_mode != PCIE_GEN3_RX ) OR ( sd_output_off == CLK_DIVRX_14 ) Error (15744): But the following assignments violate the above conditions: Error (15744): sup_mode = USER_MODE Error (15744): prot_mode = PCIE_GEN3_RX Error (15744): sd_output_off = CLK_DIVRX_6 Error (18590): The imported netlist contains settings that are not supported by the current version of the software. Import using the --timing_analysis_mode option, which ignores the errors and allows Timing Analysis to be run. Error: design::import_design -file base.qdb -overwrite failed! Error (23031): Evaluation of Tcl script /root/intelFPGA_pro/16.1/quartus/common/tcl/internal/qatm_import_design.tcl unsuccessful Error: Quartus Prime Compiler Database Interface was unsuccessful. 11 errors, 0 warnings Error: Peak virtual memory: 4554 megabytes Error: Processing ended: Mon Sep 18 02:40:32 2017 Error: Elapsed time: 00:16:10 Error: Total CPU time (on all processors): 00:16:09 Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings Error: Peak virtual memory: 1179 megabytes Error: Processing ended: Mon Sep 18 02:40:34 2017 Error: Elapsed time: 00:16:13 Error: Total CPU time (on all processors): 00:16:11 Does anyone have the similar experience or any solution/ideas for this issue? Thank you! Jiawen
