Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- Yup, the ' fixed it. Yes, the number of bytes/words I typed wasn't the correct number (9), but I was just being lazy. Thanks! --- Quote End --- Adding ' It doesnt fix my problem. I use the following line parameter reg [7:0] LCD_CMDS [0:23] = '{8'h3C, 8'h0C, 8'h01, 8'h02, 8'h48, 8'h65, 8'h6C, 8'h6C, 8'h6F, 8'h20, 8'h46, 8'h72, 8'h6F, 8'h6D, 8'h20, 8'h44, 8'h69, 8'h67, 8'h69, 8'h6C, 8'h65, 8'h6E, 8'h74, 8'h18}; and it returns=> Error (10170): Verilog HDL syntax error at PmodCLP.v(75) near text "'"; expecting an operand Need help..:) -Fahmy