Forum Discussion
Altera_Forum
Honored Contributor
12 years agoYou can read this paper (http://www.mentor.com/products/fv/resources/overview/using-strong-types-in-your-systemverilog-design-and-verification-c953bc93-075a-4b67-9e03-aab28f5bf696)to help understand the difference between packed an unpacked types.
Some tools have difficulty understanding the difference between a concatenation of bits which is a packed vector versus an unpacked array assignment, both of which use the {value1,value2} syntax. You can put a ' in front of the {} to ensure that it is recognized as an assignment pattern. See section 10.10 of the LRM But then the array assignment '{} would expect 9 unpacked array elements each 16 bits wide.