Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHere is the whole code:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity compteur_moyen_deph is port( -- Input clk : in std_logic; arazb : in std_logic; En_enteteRX : in std_logic; En_enteteRX_nbdeph : in std_logic_vector(7 downto 0); flag_moyennagetermine : in std_logic; -- Output cpt_deph : out std_logic_vector(5 downto 0):= (others => '0'); nb_deph : out std_logic_vector(7 downto 0):= (others => '0'); flag_nbdeph : out std_logic :='0'; en_finmesurereflecto : out std_logic :='0'; en_actmoyennage : out std_logic :='0' ); END compteur_moyen_deph; ARCHITECTURE ar_compteur_moyen_deph OF compteur_moyen_deph IS BEGIN PROCESS(clk,arazb) IS variable v_tempo_En_enteteRX : std_logic :='0'; variable v_tempo_flag_moyennagetermine : std_logic :='0'; variable v_attente : std_logic :='0'; variable v_reset_flag_nbdeph : std_logic :='0'; variable v_flag_nbdeph : std_logic :='0'; variable v_nb_deph : std_logic_vector (7 downto 0):= (others => '0'); variable v_cptdeph : std_logic_vector (5 downto 0):= (others => '0'); variable v_en_finmesurereflecto : std_logic :='0'; variable v_en_actmoyennage : std_logic :='0'; BEGIN --reset IF arazb ='0' THEN --variables v_tempo_En_enteteRX :='0'; v_tempo_flag_moyennagetermine :='0'; v_attente :='0'; -- modif: v_attente := '1' v_reset_flag_nbdeph :='0'; v_flag_nbdeph :='0'; v_nb_deph := (others => '0'); v_cptdeph := (others => '0') ; v_en_finmesurereflecto :='0'; v_en_actmoyennage :='0'; --output cpt_deph <= (others => '0') ; nb_deph <= (others => '0'); flag_nbdeph <='0'; en_finmesurereflecto <='0'; en_actmoyennage <='0'; ELSIF RISING_EDGE(clk) then IF (En_enteteRX ='1' AND v_tempo_En_enteteRX ='0')AND v_en_finmesurereflecto ='0' THEN v_attente_nbdeph :='1'; ELSIF v_attente_nbdeph = '1' THEN v_cptdeph := "000001"; ELSIF v_cptdeph = "000001" AND v_cptdeph <= En_enteteRX_nbdeph THEN v_nb_deph <= X"01"; v_attente_nbdeph := '0'; v_flag_nbdeph :='1'; ELSE v_flag_nbdeph := '0'; v_en_finmesurereflecto :='0'; v_attente_nbdeph := '0'; v_en_actmoyennage:= '0'; v_nb_deph <= X"FF"; --HERE MY PROBLEM, this value doesnt' change to FF.....only X"03" END IF; v_tempo_flag_moyennagetermine := flag_moyennagetermine; v_tempo_En_enteteRX := En_enteteRX ; ELSIF FALLING_EDGE(clk) then cpt_deph <= v_cptdeph; nb_deph <= v_nb_deph; -- So this output is not updated to the right value flag_nbdeph <= v_flag_nbdeph ; en_finmesurereflecto <= v_en_finmesurereflecto; en_actmoyennage <= v_en_actmoyennage; END IF; END PROCESS END ar_compteur_moyen_deph; And here is the testbench which as been done with Modelsim-altera 6.6d: