Amazing problem with a variable

Right, lets start off with the first problem - this is not software, and this is not a program. VHDL is a hardware description language - so if you try and think like software, you're probably going to have trouble. Given you're using variables everywhere, I assume you come from a software background.

I bet the easiest fix to this will be use signals instead of variables, and before that it would probably help more if you step back and draw the circuit you're trying to design on a peice of paper (its a hardware DESCRIPTION language after all - if you dont know what the circuit should be, how do you expect to describe it?). There is almost no code that needs variables rather than signals, so as a beginner, you're better off using signals.

So next question - where is the testbench?