ALU in VHDL newbi having some major issues

I don't get this, this code should add, I have one just like it for the adder alone and it adds, but mine does not, vhdl is definitely the worst langue ever.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity adder_4 is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         sum : out STD_LOGIC_VECTOR(4 downto 0)
         );
end adder_4;
architecture adder4_arc of adder_4 is
begin
    adder4 : process (a,b) is        
    variable s : std_logic_vector (4 downto 0);
    begin                                       
        s(0) := '0';
        for i in 0 to 3 loop
            sum(i) <= a(i) xor b(i) xor s(i) ;
            s(i+1) := (a(i) and b(i)) or (b(i) and s(i)) or (s(i) and a(i));
        end loop;                                                            
        sum(4) <= s(4);
    end process;
end adder4_arc;

--LIBRARY ieee ;
--USE ieee.std_logic_1164.all ;
--ENTITY fulladd IS
--	PORT ( Cin, x, y : IN STD_LOGIC ;
--				s, Cout : OUT STD_LOGIC ) ;
--END fulladd ;
--ARCHITECTURE LogicFunc OF fulladd IS
--BEGIN
--	s <= x XOR y XOR Cin ;
--	Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
--END LogicFunc ;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY alu IS
PORT(
	a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	op : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
	result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	cout : OUT STD_LOGIC;
	zero : OUT STD_LOGIC);
END alu;
ARCHITECTURE description OF alu IS
-- you fill in what goes here!!!
--COMPONENT fulladd
--		PORT ( Cin, x, y : IN  STD_LOGIC ; 
--					s, Cout : OUT STD_LOGIC ) ;
--END COMPONENT ;
SIGNAL CIN : STD_LOGIC;
SIGNAL X   : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL Y   : STD_LOGIC;
--SIGNAL C : STD_LOGIC_VECTOR(0 TO 32) ;
SIGNAL sum : STD_LOGIC_VECTOR(31 DOWNTO 0);
--variable cnt : integer := -1;
	
BEGIN
--C(0) <= op(2) ;
--	Generate_label:
--	FOR i IN 0 TO 31 GENERATE
--		stage: fulladd PORT MAP ( C(i), a(i), b(i), result(i), C(i+1)) ;
--	END GENERATE;
--	Cout <= C(32) ;
		PROCESS (op,a,b,X,CIN,sum)
		VARIABLE C : STD_LOGIC_VECTOR(32 DOWNTO 0) ;
		VARIABLE C_OUT: STD_LOGIC;
		BEGIN
			CASE op IS
				WHEN "000" =>
					result <= a AND b;
				WHEN "001" =>
					result <= a OR b;
				WHEN "010" =>
					--sum <= a + b;
					C(0) := '0';     --op(2) ;
					FOR i IN 0 DOWNTO 31 LOOP
						--sum(i) <= a(i) XOR b(i) XOR C(i) ;
						result(i) <= a(i) XOR b(i) XOR C(i) ;
						C(i+1) := (a(i) AND b(i)) OR (C(i) AND a(i)) OR (C(i) AND b(i)) ;
						--C(i+1):= C_OUT;
					END LOOP;
					cout<=C(32);
					--result<=sum;
				WHEN "110" =>
					--sum <= a - b;
					--C(0) <= op(2) ; --if carry in is one wont it mess up the operation?
					X <= ((NOT b) + 1);
					C(0) := '0';
					FOR i IN 0 DOWNTO 31 LOOP
						sum(i) <= a(i) XOR X(i) XOR C(i) ;
						C(i+1) := (a(i) AND X(i)) OR (C(i) AND a(i)) OR (C(i) AND X(i)) ;
						--C_OUT := (a(i) AND X(i)) OR (C(i) AND a(i)) OR (C(i) AND X(i)) ;
						--C(i+1):=C_OUT;
					END LOOP;
					cout<=C(32);
					--result<=sum(31 DOWNTO 0);
					result<=sum;
				WHEN "100" =>
					--sum <= a << 1;
					result <=a (30 DOWNTO 0) & '0';
				WHEN "101" =>
					--sum <= a >> 1; HOW DO I SHIFT RIGHT??
					--result <=a (0 TO 31) & '0';  -- ahh no.
				WHEN  OTHERS =>
			END CASE;	
		END PROCESS;
		
END description;