--- Quote Start ---
In what way does it "not work"? the code looks fine to me - I think you just need to write a testbench and debug it.
--- Quote End ---
Hey Trick, well it doesn't add is the problem. there seems to be something with the loop.. I can't figure it out. I did test it, using wave forms, or test bench as you call it, modelsim whatever. check out the waveform,, some other operations seem to work ok but the damn thing won't add. Also how do I shift right using a vector??
https://www.alteraforum.com/forum/attachment.php?attachmentid=8408 the 010 op corresponds to add
--LIBRARY ieee ;
--USE ieee.std_logic_1164.all ;
--ENTITY fulladd IS
-- PORT ( Cin, x, y : IN STD_LOGIC ;
-- s, Cout : OUT STD_LOGIC ) ;
--END fulladd ;
--ARCHITECTURE LogicFunc OF fulladd IS
--BEGIN
-- s <= x XOR y XOR Cin ;
-- Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
--END LogicFunc ;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY alu IS
PORT(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
op : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- in place of result
cout : OUT STD_LOGIC;
zero : OUT STD_LOGIC);
END alu;
ARCHITECTURE description OF alu IS
-- you fill in what goes here!!!
--COMPONENT fulladd
-- PORT ( Cin, x, y : IN STD_LOGIC ;
-- s, Cout : OUT STD_LOGIC ) ;
--END COMPONENT ;
SIGNAL CIN : STD_LOGIC;
SIGNAL X : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL Y : STD_LOGIC;
SIGNAL C_OUT: STD_LOGIC;
SIGNAL C : STD_LOGIC_VECTOR(0 TO 32) ;
SIGNAL sum : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
--C(0) <= op(2) ;
-- Generate_label:
-- FOR i IN 0 TO 31 GENERATE
-- stage: fulladd PORT MAP ( C(i), a(i), b(i), result(i), C(i+1)) ;
-- END GENERATE;
-- Cout <= C(32) ;
PROCESS (op,a,b)
BEGIN
CASE op IS
WHEN "000" =>
result <= a AND b;
WHEN "001" =>
result <= a OR b;
WHEN "010" =>
--sum <= a + b;
C(0) <= '0'; --op(2) ;
FOR i IN 0 DOWNTO 31 LOOP
sum(i) <= a(i) XOR b(i) XOR C(i) ;
C_OUT <= (a(i) AND b(i)) OR (C(i) AND a(i)) OR (C(i) AND b(i)) ;
C(i+1)<=C_OUT;
END LOOP;
cout<=C(32);
result<=sum;
WHEN "110" =>
--sum <= a - b;
--C(0) <= op(2) ; --if carry in is one wont it mess up the operation?
X <= ((NOT b) + 1);
C(0) <= '0';
FOR i IN 0 DOWNTO 31 LOOP
sum(i) <= a(i) XOR X(i) XOR C(i) ;
C_OUT <= (a(i) AND X(i)) OR (C(i) AND a(i)) OR (C(i) AND X(i)) ;
C(i+1)<=C_OUT;
END LOOP;
cout<=C(32);
--result<=sum(31 DOWNTO 0);
result<=sum;
WHEN "100" =>
--sum <= a << 1;
result <=a (30 DOWNTO 0) & '0';
WHEN "101" =>
--sum <= a >> 1; HOW DO I SHIFT RIGHT??
--result <=a (0 TO 31) & '0'; -- ahh no.
WHEN OTHERS =>
END CASE;
END PROCESS;
END description;
Honored Contributor
