ALU in VHDL newbi having some major issues

ok never mind I resolved the issue, but I still don't understand how to actually add.. like how do I call the adder from the if statement??

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
    PORT ( Cin, x, y : IN STD_LOGIC ;
                s, Cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
    s <= x XOR y XOR Cin ;
    Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY alu IS
PORT(
    a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    op : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
    result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- in place of result
    cout : OUT STD_LOGIC;
    zero : OUT STD_LOGIC);
END alu;
ARCHITECTURE description OF alu IS
-- you fill in what goes here!!!
COMPONENT fulladd
        PORT ( Cin, x, y : IN  STD_LOGIC ; 
                    s, Cout : OUT STD_LOGIC ) ;
END COMPONENT ;
SIGNAL C : STD_LOGIC_VECTOR(0 TO 32) ;
SIGNAL sum : STD_LOGIC_VECTOR(31 DOWNTO 0);
    
BEGIN
C(0) <= op(2) ;
    Generate_label:
    FOR i IN 0 TO 31 GENERATE
        stage: fulladd PORT MAP ( C(i), a(i), b(i), result(i), C(i+1)) ;
    END GENERATE;
    Cout <= C(32) ;
        PROCESS (op,a,b)
        BEGIN
            IF op="000" THEN
                sum <= a AND b;
            ELSIF op="001" THEN
                sum <= a OR b;
            ELSIF op="010" THEN
                --sum <= a + b;
            ELSIF op="110" THEN
                --sum <= a - b;
            ELSIF op="100" THEN
                --sum <= a << 1;
            ELSIF op="101" THEN
                --sum <= b >> 1;
            END IF;
        END PROCESS;
        
END description;

--LIBRARY ieee ;
--USE ieee.std_logic_1164.all ;
--ENTITY fulladd IS
--	PORT ( Cin, x, y : IN STD_LOGIC ;
--				s, Cout : OUT STD_LOGIC ) ;
--END fulladd ;
--ARCHITECTURE LogicFunc OF fulladd IS
--BEGIN
--	s <= x XOR y XOR Cin ;
--	Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
--END LogicFunc ;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY alu IS
PORT(
	a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	op : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
	result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- in place of result
	cout : OUT STD_LOGIC;
	zero : OUT STD_LOGIC);
END alu;
ARCHITECTURE description OF alu IS
-- you fill in what goes here!!!
--COMPONENT fulladd
--		PORT ( Cin, x, y : IN  STD_LOGIC ; 
--					s, Cout : OUT STD_LOGIC ) ;
--END COMPONENT ;
SIGNAL CIN : STD_LOGIC;
SIGNAL X   : STD_LOGIC;
SIGNAL Y   : STD_LOGIC;
SIGNAL C_OUT: STD_LOGIC;
SIGNAL C : STD_LOGIC_VECTOR(0 TO 32) ;
SIGNAL sum : STD_LOGIC_VECTOR(31 DOWNTO 0);
	
BEGIN
--C(0) <= op(2) ;
--	Generate_label:
--	FOR i IN 0 TO 31 GENERATE
--		stage: fulladd PORT MAP ( C(i), a(i), b(i), result(i), C(i+1)) ;
--	END GENERATE;
--	Cout <= C(32) ;
		PROCESS (op,a,b)
		BEGIN
			IF op="000" THEN
				sum <= a AND b;
			ELSIF op="001" THEN
				sum <= a OR b;
			ELSIF op="010" THEN
				--sum <= a + b;
				C(0) <= op(2) ;
				FOR i IN 0 DOWNTO 31 LOOP
					sum(i) <= a(i) XOR b(i) XOR C(i) ;
					C_OUT <= (a(i) AND b(i)) OR (C(i) AND a(i)) OR (C(i) AND b(i)) ;
					C(i+1)<=C_OUT;
				END LOOP;
				cout<=C(32);
				result<=sum;
			ELSIF op="110" THEN
				--sum <= a - b;
			ELSIF op="100" THEN
				--sum <= a << 1;
			ELSIF op="101" THEN
				--sum <= b >> 1;
			END IF;
		END PROCESS;
		
END description;