ALU in VHDL newbi having some major issues

ok thanks again Tricky!!..

Now I'm getting some other error for the code below. There is something wrong with my port mapping loop.

Error (10028): Can't resolve multiple constant drivers for net "result[31]" at alu.vhd(48)

Error (10029): Constant driver at alu.vhd(52)

Error (10028): Can't resolve multiple constant drivers for net "result[30]" at alu.vhd(48)

Error (10028): Can't resolve multiple constant drivers for net "result[29]" at alu.vhd(48)

Error (10028): Can't resolve multiple constant drivers for net "result[28]" at alu.vhd(48)

Error (10028): Can't resolve multiple constant drivers for net "result[27]" at alu.vhd(48)

Error (10028): Can't resolve multiple constant drivers for net "result[26]" at alu.vhd(48)

Error (10028): Can't resolve multiple constant drivers for net "result[25]" at alu.vhd(48)

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
    PORT ( Cin, x, y : IN STD_LOGIC ;
                s, Cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
    s <= x XOR y XOR Cin ;
    Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY alu IS
PORT(
    a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    op : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
    result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- in place of result
    cout : OUT STD_LOGIC;
    zero : OUT STD_LOGIC);
END alu;
ARCHITECTURE description OF alu IS
-- you fill in what goes here!!!
COMPONENT fulladd
        PORT ( Cin, x, y : IN  STD_LOGIC ; 
                    s, Cout : OUT STD_LOGIC ) ;
END COMPONENT ;
SIGNAL C : STD_LOGIC_VECTOR(0 TO 32) ;
--    SIGNAL a1:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
--    SIGNAL b1:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
--    SIGNAL result1:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
    
BEGIN
C(0) <= op(2) ;
    Generate_label:
    FOR i IN 0 TO 32-1 GENERATE
        stage: fulladd PORT MAP ( C(i), a(i), b(i), result(i), C(i+1)) ;
    END GENERATE;
    Cout <= C(32) ;
        PROCESS (op,a,b,C)
        BEGIN
            IF op="000" THEN
                result <= a AND b;
            ELSIF op="001" THEN
                result <= a OR b;
            ELSIF op="010" THEN
                --result <= a + b;
            ELSIF op="110" THEN
                result <= a - b;
            ELSIF op="100" THEN
                --result <= a << 1;
            ELSIF op="101" THEN
                --result <= b >> 1;
            END IF;
        END PROCESS;
        
END description;

Also, how the heck would I actually call the adder from the corresponding if statement??

Sorry my prof thinks we should know VHDL somehow, from our past lives I guess..