ALU in VHDL newbi having some major issues

like why doesn't this work?

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
	PORT ( Cin, x, y : IN STD_LOGIC ;
				s, Cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
	s <= x XOR y XOR Cin ;
	Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY alu IS
PORT(
	a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	op : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
	result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	cout : OUT STD_LOGIC;
	zero : OUT STD_LOGIC);
END alu;
ARCHITECTURE description OF alu IS
-- you fill in what goes here!!!
SIGNAL C : STD_LOGIC_VECTOR(0 TO 31) ;
COMPONENT fulladd
		PORT ( Cin, x, y : IN  STD_LOGIC ; 
					s, Cout : OUT STD_LOGIC ) ;
END COMPONENT ;
--	SIGNAL a1:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
--	SIGNAL b1:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
--	SIGNAL result1:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
	
BEGIN
		PROCESS (op,a,b)
		BEGIN
			IF op="000" THEN
				result <= a AND b;
			ELSIF op="001" THEN
				result <= a OR b;
			ELSIF op="010" THEN
				--result <= a + b;
stage0: fulladd PORT MAP ( Cin, a(0), b(0), S(0), C(1) ) ;
stage1: fulladd PORT MAP ( C(1), a(1), b(1), S(1), C(2) ) ;
stage3: fulladd PORT MAP ( C(2), a(2), b(2), S(2), C(3) ) ;
stage4: fulladd PORT MAP ( C(3), a(3), b(3), S(3), C(4) ) ;
stage5: fulladd PORT MAP ( C(4), a(4), b(4), S(4), C(5) ) ;
stage6: fulladd PORT MAP ( C(5), a(5), b(5), S(5), C(6) ) ;
stage7: fulladd PORT MAP ( C(6), a(6), b(6), S(6), C(7) ) ;
stage8: fulladd PORT MAP ( C(7), a(7), b(7), S(7), C(8) ) ;
stage9: fulladd PORT MAP ( C(8), a(8), b(8), S(8), C(9) ) ;
stage10: fulladd PORT MAP ( C(9), a(9), b(9), S(9), C(10) ) ;
stage11: fulladd PORT MAP ( C(10), a(10), b(10), S(10), C(11) ) ;
stage12: fulladd PORT MAP ( C(11), a(11), b(11), S(11), C(12) ) ;
stage13: fulladd PORT MAP ( C(12), a(12), b(12), S(12), C(13) ) ;
stage14: fulladd PORT MAP ( C(13), a(13), b(13), S(13), C(14) ) ;
stage15: fulladd PORT MAP ( C(14), a(14), b(14), S(14), C(15) ) ;
stage16: fulladd PORT MAP ( C(15), a(15), b(15), S(15), C(16) ) ;
stage17: fulladd PORT MAP ( C(16), a(16), b(16), S(16), C(17) ) ;
stage18: fulladd PORT MAP ( C(17), a(17), b(17), S(17), C(18) ) ;
stage19: fulladd PORT MAP ( C(18), a(18), b(18), S(18), C(19) ) ;
stage20: fulladd PORT MAP ( C(19), a(19), b(19), S(19), C(20) ) ;
stage21: fulladd PORT MAP ( C(20), a(20), b(20), S(20), C(21) ) ;
stage22: fulladd PORT MAP ( C(21), a(21), b(21), S(21), C(22) ) ;
stage23: fulladd PORT MAP ( C(22), a(22), b(22), S(22), C(23) ) ;
stage24: fulladd PORT MAP ( C(23), a(23), b(23), S(23), C(24) ) ;
stage25: fulladd PORT MAP ( C(24), a(24), b(24), S(24), C(25) ) ;
stage26: fulladd PORT MAP ( C(25), a(25), b(25), S(25), C(26) ) ;
stage27: fulladd PORT MAP ( C(26), a(26), b(26), S(26), C(27) ) ;
stage28: fulladd PORT MAP ( C(27), a(27), b(27), S(27), C(28) ) ;
stage29: fulladd PORT MAP ( C(28), a(28), b(28), S(28), C(29) ) ;
stage30: fulladd PORT MAP ( C(29), a(29), b(29), S(29), C(30) ) ;
stage31: fulladd PORT MAP ( C(30), a(30), b(30), S(30), C(31) ) ;
stage32: fulladd PORT MAP ( C(31), a(31), b(31), S(31), cout ) ;
			ELSIF op="110" THEN
				result <= a - b;
			ELSIF op="100" THEN
				--result <= a << 1;
			ELSIF op="101" THEN
				--result <= b >> 1;
			END IF;
		END PROCESS;
		
END description;