ALU in VHDL newbi having some major issues

Hey guys, let me try that again. I started from scratch. here is my code now.

Now I have the full adder sitting up there, can someone please tell me how I correctly port map the variables under the condition for adding, and use the adder that is.

I can not use the plus or minus operator like I did there, and it must be asynchronous.

Thanks

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
	PORT ( Cin, x, y : IN STD_LOGIC ;
				s, Cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
	s <= x XOR y XOR Cin ;
	Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY alu IS
PORT(
	a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	op : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
	result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	cout : OUT STD_LOGIC;
	zero : OUT STD_LOGIC);
END alu;
ARCHITECTURE description OF alu IS
-- you fill in what goes here!!!
--	SIGNAL a1:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
--	SIGNAL b1:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
--	SIGNAL result1:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
	
BEGIN
		PROCESS (op,a,b)
		BEGIN
			IF op="000" THEN
				result <= a AND b;
			ELSIF op="001" THEN
				result <= a OR b;
			ELSIF op="010" THEN
				result <= a + b;
			ELSIF op="110" THEN
				result <= a - b;
			ELSIF op="100" THEN
				--result <= a << 1;
			ELSIF op="101" THEN
				--result <= b >> 1;
			END IF;
		END PROCESS;
		
END description;