ALTPLL synthesis issue

i am using vesion 8.0 SP1, build 07/10/2008 SJ Full version.

I have tried the following things in my end and still have the issue:

A. Assigning pin location thru synthesis directive instead of thru pin planner:

input inclk0 /* synthesis chip_pin = "AA1" */; // input Clock

I got the same error.

B. Driving the PLL input thru altclkctrl in the following manner:

altclkctra pcst_altclkctrl_inst1 (

.inclk (inclk0),

.outclk (pll_clkin) );

pcst_sysclkpll pcst_sysclkpll_inst (

.areset ( PLL_RESET ),

.inclk0 ( pll_clkin ),

.c0 ( SYSCLK ),

.c1 ( CR4CLK ),

.locked ( PLL_LOCKED )

);

I got the following error:

Error: Clock input port inclk[0] of PLL "pcst_sysclkpll:pcst_sysclkpll_inst|altpll:altpll_component|pcst_sysclkpll_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

Info: Input port INCLK[0] of node "pcst_sysclkpll:pcst_sysclkpll_inst|altpll:altpll_component|pcst_sysclkpll_altpll:auto_generated|pll1" is driven by altclkctra:pcst_altclkctrl_inst1|altclkctra_altclkctrl_nie:altclkctra_altclkctrl_nie_component|wire_clkctrl1_outclk which is OUTCLK output port of CLKCTRL type node altclkctra:pcst_altclkctrl_inst1|altclkctra_altclkctrl_nie:altclkctra_altclkctrl_nie_component|clkctrl1

eventhough it is driven by CLKCTRL node, i get the same error and dont understand why.